User Terminal Principal Modem Waveform Architect - OneWeb Next

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We are looking for an experienced modem architect to become Eutelsat's technical authority on the physical layer of our next generation LEO, multi-orbit and IRIS² user terminals: a Ku and Ka band waveform that must acquire below 0 dB Es/N0, track Doppler excursions of hundreds of kilohertz with slew rates in the tens of kilohertz per second, ride through beam and satellite handovers with an interruption budget of a few tens of milliseconds, and do so within a single digit watt baseband envelope and a cost-driven silicon budget.

The target is a single-chip modem module in which the programmable PHY, the protocol stack and the host processor functions share one SoC, built from vector compute engines, a RISC-V control subsystem, hardware accelerators and an on-chip NPU. Much of the detailed implementation is carried out with external engineering and silicon partners.

Your role is to master that technology to the point of owning it: to hold the requirements, to model the link independently, to assess and challenge the design choices made on our behalf, and to accept or reject what is delivered on evidence. Knowing the platform hands-on is part of the job, not a formality, and so is the ability to reproduce a result yourself when a claim needs testing.

This is a founding role, a pioneering one and the design authority liaising directly with the vendors and internal stakeholders.

Eutelsat is building its own terminal physical layer competence and this position is where that capability starts: the models, the tooling, the test assets and the working practices are still to be created, in a programme that moves at constellation pace and relies heavily on external partners while the team is assembled.

As the capability grows, this role is the natural anchor for the modem architecture group that will be built around it. ## What you'll do - Master the platform hands-on: SDK and toolchain, micro-kernel architecture of the PHY, mapping onto signal units, scheduling and synchronisation across units, hardware abstraction layers over the FEC and signal processing engines, DMA fabric, interrupts and inter-processor communication.

You should be able to build, modify, instrument and profile PHY code yourself; - Own the terminal physical layer requirements and their traceability, from service and constellation constraints down to waveform, timing and modem parameters, and hold the specification stable through the programme; - Assess and challenge the receive chain design: acquisition strategy and its performance below 0 dB Es/N0, CFO and SFO estimation, timing recovery, carrier phase tracking under composite LO and converter phase noise, channel estimation and interpolation, equalisation, soft demapping and LLR scaling, AGC dynamics, and the loop bandwidth and stability margins behind each of them; - Verify the coding scheme and its operating point: code family and rate set, decoder mapping onto the FEC accelerator, iteration budget and early termination, LLR quantisation, and the actual position of the BLER waterfall and error floor relative to the capacity bound; - Scrutinise the transmit chain: pulse shaping and spectral mask compliance, PAPR and crest factor reduction, digital pre-distortion interface and training path, and the consistency of the EVM, ACLR, spurious and EIRP budgets from baseband to antenna aperture; - Interrogate the Doppler, delay and mobility strategy: ephemeris and GNSS aided pre-compensation of frequency and timing, closed loop refinement and timing advance, sampling frequency offset correction, the split of the residual error budget across GNSS, oscillator and tracking loops, and terminal behaviour through make-before-break transitions, re-acquisition and outage recovery; - Review the timing and clocking architecture and hold it to its targets: oscillator class and holdover drift, phase noise and jitter budget across reference, PLL, converter clocking and SYSREF distribution, GNSS and 1PPS handling, PTP client, boundary clock and grandmaster behaviour under the G.8275 profiles, and the max|TE|, MTIE and TDEV limits of the applicable G.8273.2 clock class; - Audit the fixed point design: wordlength and scaling choices, saturation and dynamic range handling, and the per-block implementation loss budget against a floating point reference; - Scrutinise the real-time partitioning across vector compute engines, accelerators and RISC-V control cores: cycles per sample and per slot, scratchpad allocation, DMA and double buffering, memory bandwidth against LPDDR or DDR, the deterministic latency chain, and the margin left for growth; - Question the co-residency of the protocol stack and host processor functions on the spare cores of the same SoC: real-time isolation, contention on shared memory and interconnect, and the margin policy that follows; - Assess where on-chip machine learning inference genuinely improves receiver performance, and under what complexity, latency and validation conditions such a function would be acceptable in an operational terminal; - Review the modem interfaces: JESD204D/E lane rates, subclass and deterministic latency, analogue IQ alternatives, sampling and clocking plan for GHz-class integrated converters, antenna control and calibration signalling, Ethernet and fronthaul, and the boundary towards the protocol stack and host processor; - Build and own an independent bit accurate reference model and the golden vectors derived from it, and use them as the basis for acceptance rather than relying on figures supplied to us; - Define the acceptance criteria and the milestone entry and exit conditions, then run or supervise the acceptance campaigns: BER and BLER against Es/N0, acquisition time distributions, sensitivity to Doppler rate and phase noise, handover interruption time, EVM and spectral compliance, timing against the applicab