Intern in the Electrical Department - Microelectronics Section

## Location ESTEC, Noordwijk, Netherlands ## Our team and mission The Avionics and EEE Division plays a pivotal role in ensuring the reliability and advancement of spacecraft avionics and component technologies. Its mission spans design assurance, qualification, and testing of EEE components, as well as radiation hardness assurance for space systems in its domain of responsibility.

The division operates specialised laboratories and provides expertise to ESA projects, industry, and research partners. It actively disseminates knowledge through internal and external training, conference participation, and tutoring of PhD students, ESA Graduate Trainees (EGTs), and National Trainees, fostering innovation and professional growth.

Components The Section is responsible for ensuring that all EEEE Components (passive & active) flown on ESA missions are suitable for their application and the environment for which they are intended, lead the development of EEEE Components and their qualification.

European Space Component Coordination (ESCC) executives and actively supporting European Cooperation for Space Standardisation (ECSS) standardisation activities. The section conducts Research and Development (R&D) activities in their domain of responsibility.

Radiation & Component Reliability The Section is responsible for assessing all aspects of EEEE Component Radiation Effects to ensure EEEE Components flown on ESA Missions are suitable for the Radiation Environment and their assigned application for the duration of the mission. It is also responsible for all EEEE Component laboratory Test and Analysis activities.

The section conducts R&D activities in their domain of responsibility and manages the EEEE Component Laboratory Facility. Actively supporting ESCC/ECSS standardisation activities.

Microelectronics The section is responsible for development and verification of all Microelectronic devices flown on ESA missions such as AI Accelerators, FPGAs, ASICs, Microprocessors, microelectronic processes, Instruction Set Architecture (ISA), radiation-aware design, prototyping and test for space‑grade microelectronics.

The section conducts R&D activities in their domain of responsibility and manages the Microelectronics Laboratory Facility. Actively supporting ECSS standardisation activities. Avionic Architecture Responsible for supporting all ESA missions in the area of Avionics Sub-System development, their verification and validation, and their qualification within the framework of the agency's strategic objectives.

Data Handling Responsible for on-board data handling sub-systems (Platform and Payload). Responsible for developing and qualifying equipment for data acquisition, processing, and distribution (buses, interfaces, mass‑memory, data‑processing chains, remote interface units, etc.). on-Board data processing is an important focus of the section including development of turn-key AI HW solutions for ESA Missions.

The section conducts R&D activities in their domain of responsibility and manages the Data Handling Laboratory Facility. Actively supporting ECSS/CCSDS standardisation activities. Flight Software This section designs and maintains flight software for spacecraft control and payload management. It addresses real-time operating systems, fault detection and recovery, and software validation frameworks.

The team also explores advanced concepts such as AI-assisted on-board processing, ensuring adaptability and resilience in increasingly complex missions. The section conducts R&D activities in their domain of responsibility and manages the Flight Software Laboratory Facility. Actively supporting ECSS/CCSDS standardisation activities.

Candidates interested are encouraged to visit the ESA website: http://www.esa.int ## 1) Topic 1: Smarter Verification for Space Systems: Evaluating AI Approaches for FPGA Design Validation The increasing complexity of FPGA and ASIC developments for space applications makes digital design verification one of the most resource-intensive phases of the development cycle.

At the same time, recent advances in Artificial Intelligence (AI), particularly Large Language Models (LLMs), offer new opportunities to automate verification activities and improve engineering productivity. This internship will investigate the applicability of AI tools to support the verification of digital designs used in future space systems.

The work will evaluate how AI can assist engineers in creating and maintaining verification environments using modern frameworks such as UVVM and cocotb. Representative case studies may include RISC-V processors, communication interfaces, digital signal-processing functions, and hardware accelerators.

The study will compare traditional and AI-assisted verification approaches, focusing on tasks such as testbench generation, test creation, debugging, coverage analysis, and documentation. Particular attention will be given to the trade-offs between UVVM's VHDL-based methodology and cocotb's Python-based flexibility.

The outcome will be a set of recommendations for the adoption of AI-assisted verification techniques in future ESA microelectronics developments. ## 2) Topic 2: Towards fast FPGA Demonstrators: AI-Assisted IP Integration and Automated System Assembly for ESA Microelectronics ESA and European developments have produced a growing portfolio of reusable FPGA and ASIC Intellectual Property (IP) cores.

However, integrating these assets into complete systems often requires significant manual effort, limiting reuse and increasing development time. This internship will investigate how Artificial Intelligence (AI) can support the integration and reuse of digital IP cores for FPGA-based demonstrators.

The work will explore how AI can help engineers understand IP capabilities, identify compatible interfaces, generate integration artefacts, propose system architectures, detect integration issues, and produce technical documentation.

Particular attention will be given to the role of machine-readable IP descriptions, including the feasibility of using standards such as IP-XACT and tools such as Kactus2 to enable AI-assisted design assembly. Representative case studies may include communication interfaces, processor subsystems, digital signal-processing functions, and other ESA-developed IP blocks; with special focus on European FPGAs design flows.

The resulting workflows will be evaluated through the creation and deployment of FPGA demonstrators on the TEC-EDM FPGA Farm.

The outcome will be recommendations for future ESA digital engineering practices, enabling faster IP reuse, automated demonstrator generation, and more efficient validation of microelectronics developments. ## Behavioural competencies Result Orientation Operational Efficiency Fostering Cooperation Relationship Management Continuous Improvement Forward Thinking For more information, please refer to ESA Core Behavioural Competencies guidebook ## Education You must be a university student, preferably in your final or second-to-last year of university course at Master's level.

In addition, you must be able to prove that you will be enrolled at your university for the entire duration of the internship. ## Additional requirements The working languages of the Agency are English and French. A good knowledge of one of these is required. Knowledge of another ESA Member State language is an asset.

During the interview, your motivation for applying to this role will be explored. ## Diversity, Equity and Inclusiveness ESA is an equal opportunity employer, committed to achieving diversity within the workforce and creating an inclusive working environment.

We therefore welcome applications from all qualified candidates irrespective of gender, sexual orientation, ethnicity, religious beliefs, age, disability or other characteristics. At the Agency we value diversity, and we welcome people with disabilities. Whenever possible, we seek to accommodate